半導体記憶装置

Semiconductor storage device

Abstract

(57)【要約】 【課題】メモリセルアレイ端の領域のエッチング精度の 低下に起因した不良を防ぐことができる半導体記憶装置 を提供することを目的としている。 【解決手段】メモリセルM 1 〜M 8 を複数個接続した第 1のメモリセルユニットにより構成された第1のブロッ ク2−0,2−Nと、メモリセルM 1 〜M 8 を複数個接 続した第2のメモリセルユニットにより構成された第2 のブロック2−1〜2−(N−1)とを有し、両端に前 記第1のブロックを、他の部分には前記第2のブロック を配設してメモリセルアレイ2を構成している。そし て、前記第1のメモリセルユニットの前記メモリセルア レイ端側の構成が前記第2のメモリセルユニットと異な ることを特徴とする。メモリセルアレイ端の領域のエッ チング精度の低下に起因した不良を防ぐことができ、チ ップサイズの増加をほとんど招くことなく、歩留まりが 高く且つ動作の信頼性の高い動作を実現できる。
PROBLEM TO BE SOLVED: To prevent failures caused by the lowering of the etching accuracy in the end region of a memory cell array. SOLUTION: A semiconductor storage device is constituted by arranging first blocks 2-0 and 2-N composed of first memory cell units, in each of which a plurality of memory cells M1-M8 are connected at both ends and second blocks 2-1 to 2-(N-1) composed of second memory cell units, in each of which a plurality of memory cells M1-M8 are connected between the first blocks 2-0 and 2-M. The constitution of each first memory cell unit on the end side of a memory cell array is made different from that of each memory cell unit on the end side of the memory cell array. Consequently, the failure caused by the lowering of the etching accuracy in the end region of the memory cell array and the yield and operational reliability of the storage device can be improved with hardly causing increase in the chip size of the device.

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Cited By (13)

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    JP-2006313873-ANovember 16, 2006Hynix Semiconductor Inc, 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.プログラム速度の均一な不揮発性メモリ素子
    JP-2007335821-ADecember 27, 2007Ricoh Co Ltd, 株式会社リコーSemiconductor memory device
    JP-2008234815-AOctober 02, 2008Toshiba Corp, 株式会社東芝Semiconductor memory device
    US-6979860-B2December 27, 2005Kabushiki Kaisha ToshibaSemiconductor device and manufacturing method thereof
    US-7241651-B2July 10, 2007Kabushiki Kaisha ToshibaSemiconductor device manufacturing method
    US-7263000-B2August 28, 2007Kabushiki Kaisha ToshibaNAND type memory with dummy cells adjacent to select transistors being biased at different voltage during data erase
    US-7422937-B2September 09, 2008Kabushiki Kaisha ToshibaSemiconductor device and manufacturing method thereof
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    US-8482984-B2July 09, 2013Kabushiki Kaisha ToshibaNonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell
    US-8879326-B2November 04, 2014Kabushiki Kaisha ToshibaNonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell